Scalable Low Power Accelerator for Sparse Recurrent Neural Network

Panshi JIN; Junjie LI; Jingyi WANG; Pengchong LI; Lei XING; Xiaodong LI

doi:10.11959/j.issn.2096-8930.2023045

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Scalable Low Power Accelerator for Sparse Recurrent Neural Network

Applications | 更新时间：2024-06-03

- Scalable Low Power Accelerator for Sparse Recurrent Neural Network
- Space-Integrated-Ground Information Networks Vol. 4, Issue 4, Pages: 79-85(2023)
- 作者机构：
  
  1. 中国建设银行股份有限公司，北京 100034
  2. 建信金融科技有限责任公司，上海 321004
  3. 浪潮电子信息产业股份有限公司，山东济南 250000
- 作者简介：
- 基金信息：
- DOI：10.11959/j.issn.2096-8930.2023045
  CLC： TP393
- Online First：2023-12，
  
  Published：20 December 2023
- 稿件说明：
移动端阅览
Panshi JIN, Junjie LI, Jingyi WANG, et al. Scalable Low Power Accelerator for Sparse Recurrent Neural Network[J]. Space-Integrated-Ground Information Networks, 2023, 4(4): 79-85.
DOI：

Panshi JIN, Junjie LI, Jingyi WANG, et al. Scalable Low Power Accelerator for Sparse Recurrent Neural Network[J]. Space-Integrated-Ground Information Networks, 2023, 4(4): 79-85. DOI： 10.11959/j.issn.2096-8930.2023045.

摘要

利用银行网点内边缘计算设备进行客流分析、安全保护、风险防控等应用日益广泛，其中 AI 推理芯片的性能和功耗已经成为边缘计算设备选型的一个非常重要的因素。针对递归神经网络由数据依赖性和低数据重用性导致的功耗大、推理性能弱、能效低，难以在低功耗平台上处理等问题，利用FPGA实现了一种电压可扩展的稀疏循环神经网络（RNN）低功率加速器，并在边缘设计算设备上进行了验证。首先，对稀疏RNN进行分析并采用网络压缩的方法设计了处理阵列；其次，由于稀疏RNN的工作负载不平衡，引入电压缩放方法以保持低功耗和高吞吐量。试验表明，该方法可以显著提高系统的RNN 推理速度并降低芯片的处理功耗。

Abstract

The use of edge computing devices in bank outlets for passenger flow analysis

security protection

risk prevention and control is increasingly widespread

among which the performance and power consumption of AI reasoning chips have become a very important factor in the selection of edge computing devices.Aiming at the problems of recurrent neural network

such as high power consumption

weak reasoning performance and low energy efficiency

which were caused by data dependence and low data reusability

this paper realized a sparse RNN low-power accelerator with scalable voltage by using FPGA

and verifies it on the edge design and calculation equipment.Firstly

the sparse -RNN was analyzed and the processing array was designed by network compression.Secondly

due to the unbalanced workload of sparse RNN

it introduced voltage scaling method to maintain low power consumption and high throughput.Experiments show that this method could significantly improve the RNN reasoning speed of the system and reduce the processing power consumption of the chip.

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references

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